In the operation of a dynamic random access memories ("DRAMs"), specific functions must occur in a predetermined sequence. These functions are generally performed responsive to respective command signals issued by a command generator. The timing of the command signals is generally controlled by a clock signal either registered to an edge of the clock signal or occurring a predetermined time after an edge of the clock signal. The rate at which the DRAM may process commands is limited by the amount of time it takes to perform functions responsive to the commands. For most functions, the minimum times to perform the functions are specified by the manufacturer of the DRAM. however, since the commands are generally issued responsive to clock signals, the amount of time that the DRAM has to perform its functions is controlled by the clock speed. For example, as illustrated in FIG. 1A, a memory read command 10 is issued by a conventional memory controller and is registered with a clock signal 12 at time t.sub.0. As further shown in FIG. 1A, it requires four clock cycles to complete the read operation because of the many operations that must occur in a DRAM before data can be read from the DRAM. Thus, a data bit 14 is not present on the data bus until time t.sub.1. The elapsed time from issuing the read command 10 to the complete processing of the command by applying the data bit 14 to the data bus is therefore .DELTA.t.sub.a. The elapsed time could be reduced by increasing the speed of the clock 12. However, regardless of the speed of the clock, the DRAM requires a certain minimum time to complete its functions. Speeding the clock up beyond that point will not reduce the amount of time required to perform those functions.
Although DRAMs are operating at optimum speed when the clock is at or near its maximum speed, they operate a far from optimum speed responsive to slower clock speeds. With reference to FIG. 1B, a clock signal 20 has a speed or frequency only half that of the clock 12 in FIG. 1A. Once again, a read command 22 is registered with the clock 20 at time t.sub.0, and a data bit 24 is applied to the data bus four clock cycles later. However, because of the slower speed clock 20, the data bit 24 is not applied to the data bus until t.sub.2. As a result of the slower clock speed, the elapsed time between issuing of the read command 22 and complete processing of the command is .DELTA.t.sub.b which is twice the duration of .DELTA.t.sub.a. Thus, by employing a fixed relationship between a clock signal and the issuing of command signals, conventional DRAMs often operate at far from optimum speed when they receive a relatively slow clock signal.
It will be understood by one skilled in the art that the timing diagrams of FIGS. 1A and 1B omit a large number of other signals applied to the DRAM. These signals have been omitted for purposes of brevity. Also, one skilled in the art will understand that the command signals 10, 22 are, in reality, composed of a combination of other signals which are commonly referred to as simply a command. The exact nature of these signals will depend on the nature of the DRAM, but the principle explained above is applicable to all type of DRAMs, including asynchronous DRAMs, synchronous DRAMs, and packetized DRAMs. Also, although the problem resulting from issuing command signals according to a fixed relationship with the clock signal has been explained with reference to DRAMs, the explanation of the problem as well as the solution provided by the preferred embodiment of the invention are applicable to other integrated circuits that issue command signals or the like responsive to a clock signal.